module top_module (
    input clk,
    input areset,
    input x,
    output z
); 
	localparam IDLE=2'b00;
	localparam S1=2'b01;
	localparam S2=2'b11;
	localparam S3=2'b10;
	
	reg[1:0]state;
	reg[1:0]next_state;
	
	always@(posedge clk or posedge areset)begin
		if(areset)begin
			state<=IDLE;
		end
		else begin
			state<=next_state;
		end
	end
	
	always@(*)begin
		case(state)
			IDLE:begin 
				next_state=(x)?S1:IDLE;
				z=1'b0;
			end
			S1:begin
				next_state=(x)?S2:S1;
				z=1'b1;
			end
			S2:begin
				next_state=(x)?S2:S1;
				z=1'b0;
			end
			default:begin
				next_state=next_state ;
				z=z;
			end
		endcase
	end
	
endmodule